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Archive for the 'Coherent DSP' Category

  • July 08, 2026

    Scaling AI Networks with Intelligent Ethernet: Validating Packet Trimming, Auto Load Balancing (ALB) and Ultra Ethernet Transport (UET) on ³Ô¹ÏºÚÁÏ Teralynx

    By Vikram Dattatri, Senior Engineer, Cloud Platform Group, ³Ô¹ÏºÚÁÏ

    Packet trimming doesn¡¯t prevent traffic losses from occurring; instead, it streamlines the process for recovering them. It is also one of many technologies ³Ô¹ÏºÚÁÏ is developing to optimize networks for the AI era.

    Artificial intelligence infrastructure is driving a fundamental shift in how data center networks are designed, validated, and deployed. As clusters scale to thousands¡ªor even tens of thousands¡ªof GPUs, the network is no longer just a connectivity layer. It becomes a tightly coupled component of the compute system, directly impacting job completion time, efficiency and overall cost.

    To address these evolving requirements, Ethernet is undergoing a transformation. At OFC 2026, ³Ô¹ÏºÚÁÏ and Keysight Technologies demonstrated (see the video below) how next-generation Ethernet fabrics can meet the demands of AI workloads through a combination of advanced features and realistic validation. Leveraging Keysight¡¯s and , the collaboration showcased how the?³Ô¹ÏºÚÁÏ? Teralynx? switch fabric?supports emerging Ultra Ethernet Consortium (UEC) capabilities, with a particular focus on packet trimming, Auto Load Balancing (ALB) and Ultra Ethernet Transport (UET).

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  • June 17, 2026

    Plasmonics: A Path to Higher Bandwidth in Optics in the AI Era

    By Claudia Hoessbacher, Senior Director, and Wolfgang Heni, Director, Optical Engineering, ³Ô¹ÏºÚÁÏ

    Plasmons have been used to accelerate drug discovery, enhance the sensitivity of sensors and even .

    Ongoing research at ³Ô¹ÏºÚÁÏ seeks to harness them to improve the performance of optical networks for the AI era. Plasmonics, a technology that leverages the properties of surface plasmon polaritons (SPPs), provides a promising pathway for enhancing the roadmap of silicon photonic (SiPho) light engines, a critical component inside optical modules.

    Plasmonic-based SiPho light engines could support modules operating at 3.2T and beyond while consuming a fraction of the space and power per bit of modules based on existing technologies. Manufacturers could leverage foundry process technologies for scaling production.

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  • May 28, 2026

    Open CPX Sets the Stage for More Flexible, Scalable Connectivity

    By George Hervey, Associate Vice President, Cloud Switch Marketing, ³Ô¹ÏºÚÁÏ

    Co-packaged connectivity is coming. The (Co-packaging Multisource Agreement) is working to simplify adoption.

    The consortium, which includes ³Ô¹ÏºÚÁÏ and other leaders in connectivity, is developing specifications and standards for solutions for integrating near-packaged optical (NPO) and/or co-packaged optical (CPO) technology into switches and servers in scalable, repeatable ways. Members are also working to support interoperability with co-packaged copper (CPC).

    The idea is to give data center service providers, equipment manufacturers and others a unified framework for next-generation connectivity to accelerate innovation and meet the surging demand for these technologies. Fewer than one million near- and co-packaged ports shipped in 2025, according to LightCounting; by 2030, shipments are projected to surpass 100 million ports per year.1 Standards that can ensure predictability and flexibility will be critical in enabling this expected growth.

    ¡°The initial target of the MSA will be to develop an optimized optical engine with a defined pluggable socket and electrical connector system supporting high speed and high-density connectivity between a switch or processor and co-packaged and near-package interconnects,¡± the Open CPX MSA website states. ¡°The specifications will define connector mechanicals, thermals, electrical pinout, mechanical form factors, electrical, optical, and management interface specifications to ensure interoperability between multiple vendors of Open CPX.¡±

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  • May 26, 2026

    224G Long-Range SerDes for Scale-up and Scale-inside

    By Aatreya Chakravarti, Senior Staff Engineer, Custom Cloud Solutions, ³Ô¹ÏºÚÁÏ

    In dense computing environments, copper continues to surprise.

    and ³Ô¹ÏºÚÁÏ teamed up on a compelling demonstration at OFC 2026 highlighting how long-reach serializer/deserializer (LR SerDes) technology can be integrated with co-packaged copper (CPC) and other connectivity solutions to create high-performance, high-bandwidth scale-inside fabrics for linking chips within server or switch trays or scale-up or scale-out networks linking trays within a rack. In other words, connections that can traverse an entire rack with low bit error rates (BER) that minimize power, cost, volumetric space and component count.

    The demo is based on a ³Ô¹ÏºÚÁÏ 3nm 224G LR SerDes driving signals across a CPC-Backplane-CPC channel composed of a 0.75-meter, thin-gauge (31 AWG) KOOLIO?CPC solution from Luxshare-Tech, a 1-meter Luxshare-Tech Intrepid? APEX backplane solution (26 AWG) and another 0.75-meter KOOLIO? CPC solution for a cumulative transmission distance of 2.5 meters. Data gets transmitted across eight SerDes lanes. End-to-end bump losses come to 48dB with lane BERs reaching 1e-11, far lower than the specification.1 :

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  • May 21, 2026

    PCIe-based Switching for AI Scale-up Networks

    By Krishna Mallampati, Senior Director of Product Marketing, Data Center Switching, ³Ô¹ÏºÚÁÏ

    Peripheral Component Interconnect Express (PCIe)? is the world¡¯s most popular interconnect for connections between chips in a shared system, while ensuring low latency, and it is well suited to be deployed for the scale-up domain. Scale-up networks extend across racks and possess hundreds of processors; low latency and high bandwidth are required in these systems that make up the foundation of AI data centers.

    ³Ô¹ÏºÚÁÏ demonstrates the industry¡¯s first 260-lane PCIe 6.0 switch in the video below, marking a new performance standard for PCIe scale-up performance¡ª256 lanes of data traffic (plus four lanes for management) is the industry¡¯s highest radix for a PCIe switch.

    Traditional PCIe switch architectures require multiple devices to scale, racking up complexity and cost. However, the ³Ô¹ÏºÚÁÏ Structera S PCIe switch flattens the network and eliminates the need for multiple smaller switches in a large scale-up system. This enables higher density, lower latency and overall increased system efficiency, making it an optimal solution for hyperscale operators.

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