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Posts Tagged 'AI'

• September 15, 2026

  

  

  

  Breaking Through the KV Cache Memory Wall with DPU-powered Network Storage

  By Chander Chadha, Director of Product Marketing, Storage Products, ³Ô¹ÏºÚÁÏ

  As AI models grow larger and inference workloads scale, larger models, longer context windows and growing KV caches are driving demands on memory resources. Traditional CPU-centric networked JBOF (Just Bunch of Flash) can¡¯t keep pace with the throughput, latency, and efficiency requirements of these modern AI clusters.

  DPU (data processing unit) -based storage is a compelling alternative to traditional storage, acting as the broker between the network and SSD for remote storage. By offloading storage, networking and security processing from the host CPU onto a dedicated DPU, AI infrastructure can move data closer to compute, reduce latency, and free up valuable CPU cycles for AI workloads.

  To address this need, ³Ô¹ÏºÚÁÏ offers the OCTEON DPU family, purpose-built for hyperscale cloud workloads and data center applications, extending its use specifically into network storage acceleration for AI environments.

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• August 05, 2026

  

  

  

  Accelerating AI Infrastructure with ³Ô¹ÏºÚÁÏ Structera A and SK hynix CXL Memory: Enabling Efficient Near-Memory Processing

  By Khurram Malik, Associate Vice President, Custom Cloud Solutions, ³Ô¹ÏºÚÁÏ, and Kangkyu Park, Vice President, System Architecture, SK hynix

  The rapid growth of AI workloads is creating unprecedented demands on data center architectures. Modern AI applications, including large language models (LLMs), generative AI, recommendation systems, and high-performance computing, require significantly higher memory capacity, bandwidth, and efficiency.

  Traditional compute-centric architectures are increasingly limited by the movement of data between processors and memory. As AI models continue to scale, excessive data movement creates performance bottlenecks, increases latency, and drives higher power consumption.

  To address these challenges, the industry is moving toward memory-centric computing architectures enabled by Compute Express Link? (CXL?). CXL enables flexible memory expansion, memory pooling, and new system architectures that allow compute resources to operate more efficiently.

  ³Ô¹ÏºÚÁÏ and SK hynix are collaborating to enable the next generation of memory-centric computing by combining ³Ô¹ÏºÚÁÏ? Structera? A CXL-based near-memory acceleration technology with . Together, ³Ô¹ÏºÚÁÏ and SK hynix are helping accelerate the adoption of CXL-enabled architectures for AI data centers by delivering a highly efficient and scalable approach to memory processing.

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• August 04, 2026

  

  

  

  Photonic Fabric? Technology: How Optical Connectivity Enables the Next Generation of AI Infrastructure

  By Ravi Mahatme, Senior Director, Product Management, Photonic Fabric Business Unit, ³Ô¹ÏºÚÁÏ

  AI infrastructure is entering a new architectural era. As AI inference scales, performance increasingly depends not simply on adding more compute, but on how efficiently compute, memory and connectivity operate together as one unified AI infrastructure system. Modern AI inference workloads are insatiable consumers of memory. Large language models, reasoning models and agentic AI applications require rapid access to model parameters, embeddings and rapidly growing key-value (KV) caches that preserve conversational context. These working data sets are growing into the hundreds of gigabytes, and increasingly terabytes, making memory capacity, bandwidth and latency just as important as accelerator performance. As AI infrastructure scales, overall system performance increasingly depends on how efficiently accelerators can access, move and utilize memory resources rather than simply adding more compute.

  Why AI Needs a New Memory Tier

  Today's AI memory hierarchy was never designed for inference at the scale modern workloads demand. High bandwidth memory (HBM) attached directly to GPUs delivers exceptional performance but remains expensive and capacity constrained. System DRAM provides larger memory pools but cannot economically scale alongside every accelerator. NVMe SSDs offer abundant capacity, yet their latency makes them unsuitable for serving active inference workloads.

  This challenge is especially visible in large language models, where growing KV caches must remain readily accessible to avoid repeatedly recomputing previous tokens. Keeping these caches entirely in HBM is prohibitively expensive, while moving them to storage introduces latency that reduces token generation performance. The result is that GPUs increasingly spend valuable cycles waiting for data rather than performing inference.

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• June 24, 2026

  

  

  

  Structera X and A CXL Compression: Making Every Gigabyte Count

  By Arifur Rahman, Director of Product Marketing, Custom Cloud Solutions, ³Ô¹ÏºÚÁÏ

  

  Modern AI workloads are insatiable consumers of memory. Deep learning recommendation models (DLRM), large language model (LLM) inference, in-memory databases and vector search engines all share a common bottleneck: there is never enough DRAM, and what exists is very expensive.

  At today's spot prices¡ª$27¨C$37 per GB for server-grade DDR5 RDIMMs1¡ªa 12TB memory pool requires nearly half a million dollars in DRAM alone. Meanwhile, AI infrastructure buildouts are consuming server DRAM capacity faster than fabs can produce it, driving prices up 300¨C400% since mid-2025.^{1, 2}

  CXL memory expansion was supposed to solve this. And it does¡ªbut there's a subtler lever that most solutions ignore: the data sitting in that memory is compressible, and most CXL controllers don't touch it.

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• June 17, 2026

  

  

  

  Plasmonics: A Path to Higher Bandwidth in Optics in the AI Era

  By Claudia Hoessbacher, Senior Director, and Wolfgang Heni, Director, Optical Engineering, ³Ô¹ÏºÚÁÏ

  Plasmons have been used to accelerate drug discovery, enhance the sensitivity of sensors and even .

  Ongoing research at ³Ô¹ÏºÚÁÏ seeks to harness them to improve the performance of optical networks for the AI era. Plasmonics, a technology that leverages the properties of surface plasmon polaritons (SPPs), provides a promising pathway for enhancing the roadmap of silicon photonic (SiPho) light engines, a critical component inside optical modules.

  Plasmonic-based SiPho light engines could support modules operating at 3.2T and beyond while consuming a fraction of the space and power per bit of modules based on existing technologies. Manufacturers could leverage foundry process technologies for scaling production.

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• Breaking Through the KV Cache Memory Wall with DPU-powered Network Storage
• ³Ô¹ÏºÚÁÏ Demonstrates Scalable CXL Memory Infrastructure with Intel
• ³Ô¹ÏºÚÁÏ Structera X Extends CXL Interoperability to NVIDIA Vera
• Engineered to Collaborate: Robot Racing as a Microcosm of ³Ô¹ÏºÚÁÏ