Posts Tagged 'Cloud'
-
September 10, 2026
³Ô¹ÏºÚÁÏ Demonstrates Scalable CXL Memory Infrastructure with Intel
By Khurram Malik, Associate Vice President, Custom Cloud Solutions, ³Ô¹ÏºÚÁÏ
The rapid growth of AI is creating unprecedented demand for memory capacity. As models get larger and workloads become more data-intensive, traditional server architectures are increasingly challenged to scale memory efficiently.
At Flash Memory Summit (FMS), ³Ô¹ÏºÚÁÏ demonstrated how CXL can enable a more flexible and scalable approach to memory infrastructure, showcasing an end-to-end architecture at the ? booth.
The demonstration combined an Intel platform with three ³Ô¹ÏºÚÁÏ? technologies: Structera? X CXL memory expander, Structera? S CXL switch and Alaska? P PCIe retimer. Together, they demonstrated how memory expansion, CXL switching and high-speed PCIe connectivity can work together within a real server platform.
-
September 09, 2026
³Ô¹ÏºÚÁÏ Structera X Extends CXL Interoperability to NVIDIA Vera
By Arifur Rahman, Director of Product Marketing, Custom Cloud Solutions, ³Ô¹ÏºÚÁÏ
Memory has become the defining constraint of modern AI infrastructure. Large language models, in-memory databases, and deep learning recommendation models all share the same bottleneck: there is never enough DRAM. Compute Express Link (CXL) was designed to break that bottleneck but a CXL memory expander is only as valuable as the breadth of platforms it can run on.
That is why ecosystem enablement is a core pillar of ³Ô¹ÏºÚÁÏ's CXL strategy. Today we are marking a new milestone: successful interoperability of the ³Ô¹ÏºÚÁÏ? Structera? X CXL memory-expansion controller with the .
-
August 04, 2026
³Ô¹ÏºÚÁÏ Structera? X, A and S: A Comprehensive CXL Portfolio Powering AI Memory Innovation
By Khurram Malik, AVP, Data Center Memory and Storage Solutions, ³Ô¹ÏºÚÁÏ
CXL has become one of the most important technologies shaping AI infrastructure. As hyperscalers race to deploy larger AI models, longer context windows and increasingly memory-intensive inference workloads, memory capacity and bandwidth have emerged as critical constraints on performance, efficiency and scaling. At the same time, CXL adoption is reaching an inflection point, moving from evaluation into real-world deployment across hyperscale environments.
³Ô¹ÏºÚÁÏ is leading this transition with Structera? X memory expansion solutions developed alongside the world¡¯s leading hyperscalers. The story begins with the shipping of Structera X 2404 and 2504 platforms, which have enabled hyperscalers to expand memory resources more efficiently, including extending the useful life of existing DDR4 investments while powering demanding AI workloads.
Structera X is not a series of disconnected product eras¡ªit is a single, continuous architectural evolution. Today¡¯s generation is already delivering real hyperscaler deployments, ecosystem maturity and a compelling TCO advantage. From that foundation, ³Ô¹ÏºÚÁÏ is extending the architecture toward the next phase of AI infrastructure innovation, adding capabilities enabled by the evolving CXL 3.2 ecosystem, PCIe Gen 6 connectivity and more advanced multi-host memory sharing architectures. These advancements will create larger, more flexible memory pools, enabling more efficient sharing of resources across servers and improving infrastructure utilization at hyperscale. As the architecture advances, ³Ô¹ÏºÚÁÏ is driving it toward higher bandwidth, deeper data optimization and increasingly disaggregated memory environments built to meet the growing demands of AI workloads.
-
May 28, 2026
Open CPX Sets the Stage for More Flexible, Scalable Connectivity
By George Hervey, Associate Vice President, Cloud Switch Marketing, ³Ô¹ÏºÚÁÏ
Co-packaged connectivity is coming. The (Co-packaging Multisource Agreement) is working to simplify adoption.
The consortium, which includes ³Ô¹ÏºÚÁÏ and other leaders in connectivity, is developing specifications and standards for solutions for integrating near-packaged optical (NPO) and/or co-packaged optical (CPO) technology into switches and servers in scalable, repeatable ways. Members are also working to support interoperability with co-packaged copper (CPC).
The idea is to give data center service providers, equipment manufacturers and others a unified framework for next-generation connectivity to accelerate innovation and meet the surging demand for these technologies. Fewer than one million near- and co-packaged ports shipped in 2025, according to LightCounting; by 2030, shipments are projected to surpass 100 million ports per year.1 Standards that can ensure predictability and flexibility will be critical in enabling this expected growth.
¡°The initial target of the MSA will be to develop an optimized optical engine with a defined pluggable socket and electrical connector system supporting high speed and high-density connectivity between a switch or processor and co-packaged and near-package interconnects,¡± the Open CPX MSA website states. ¡°The specifications will define connector mechanicals, thermals, electrical pinout, mechanical form factors, electrical, optical, and management interface specifications to ensure interoperability between multiple vendors of Open CPX.¡±
-
July 16, 2020
The Need for Speed at the Edge
By George Hervey, Principal Architect, ³Ô¹ÏºÚÁÏ
In the previous TIPS to Living on the Edge, we looked at the trend of driving network intelligence to the edge. With the capacity enabled by the latest wireless networks, like 5G, the infrastructure will enable the development of innovative applications. These applications often employ a high-frequency activity model, for example video or sensors, where the activities are often initiated by the devices themselves generating massive amounts of data moving across the network infrastructure. Cisco¡¯s VNI Forecast Highlights predicts that global business mobile data traffic will grow six-fold from 2017 to 2022, or at an annual growth rate of 42 percent1, requiring a performance upgrade of the network.
Recent Posts
- ³Ô¹ÏºÚÁÏ Montage: Stories of Recharging and Finding Meaning
- Breaking Through the KV Cache Memory Wall with DPU-powered Network Storage
- ³Ô¹ÏºÚÁÏ Demonstrates Scalable CXL Memory Infrastructure with Intel
- ³Ô¹ÏºÚÁÏ Structera X Extends CXL Interoperability to NVIDIA Vera
- Engineered to Collaborate: Robot Racing as a Microcosm of ³Ô¹ÏºÚÁÏ