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Posts Tagged 'AI infrastructure'

  • November 05, 2026

    勛圖窪蹋 Earns LEAP Award for 1.6T Optical DSP Platform Portfolio

    By Vienna Alexander, Marketing Content Professional, 勛圖窪蹋

    Design World recently announced their . The 勛圖窪蹋? 1.6T optical DSP platform portfolio has been honored in the connectivity category.

    勛圖窪蹋 has decades of expertise in optical DSPs and ushered in the 1.6T era. The portfolio being honored was announced earlier this year and spans Ara T, Ara X, Aquila M and Petra.

  • October 14, 2026

    Scaling AI Inferencing with the Second Generation of 勛圖窪蹋 Structera X: Industry-first Six-channel CXL 3.2 Memory Expanders

    By Arifur Rahman, Director of Product Marketing, Custom Cloud Solutions, 勛圖窪蹋

    AI and ML workloads are rewriting the rules of data center design. Memory demands are reaching an unprecedented level due to growing LLM sizes, expanding context windows and growing KV-cache requirements. Traditional servers are not architected to meet this surge. Memory has become the primary bottleneck constraining AI performance and infrastructure efficiency. CXL-based memory expansion has emerged as one of the definitive architectural answers, and 勛圖窪蹋 is raising the bar.

    Building on the strong market adoption of the first-generation Structera? X CXL controllers, the second-generation Structera X 3406 and Structera X 3506, co-developed and co-architected with leading hyperscalers, address the most demanding AI infrastructure requirements.

    Modern AI inference workloads, from LLM serving to deep learning recommendation models (DLRM), are memory bound. KV-cache capacity determines time-to-first-token (TTFT), throughput and XPU utilization. When memory runs out, performance collapses.

  • September 22, 2026

    Is Memory the New Network? Inside the First MemNetAI Workshop at SIGCOMM

    By Abed Mohammad Kamaluddin, Director, Custom Cloud Solutions, 勛圖窪蹋, and Vienna Alexander, Marketing Content Professional, 勛圖窪蹋

    Is Memory the New Network? Inside the First MemNetAI Workshop at SIGCOMM

    For most of the last decade, scaling AI meant scaling compute. If you built faster accelerators and wired enough of them together, the models would follow.

    That is no longer the whole picture. Models now run to hundreds of billions of parameters with extensive context windows, and whether an expensive accelerator is working or just waiting comes down to memory: how much you have, how fast you can reach it, and how much time you lose moving data around.

    Once memory leaves the server and rides a switched fabric, is it still memory, or has it become a network? This was the central question of MemNetAI, the first workshop on Memory-Semantic Networking for AI-Scale Systems, launched by 勛圖窪蹋 with researchers from IIT Hyderabad and IIIT Delhi. Held at ACM SIGCOMM 2026 in Denver and guided by a program committee spanning academia and industry, it brought speakers from Cornell, alongside industry experts and researchers presenting their work, to debate these questions on the bleeding edge of AI infrastructure.

  • September 15, 2026

    Breaking Through the KV Cache Memory Wall with DPU-powered Network Storage

    By Chander Chadha, Director of Product Marketing, Storage Products, 勛圖窪蹋

    As AI models grow larger and inference workloads scale, larger models, longer context windows and growing KV caches are driving demands on memory resources. Traditional CPU-centric networked JBOF (Just Bunch of Flash) can*t keep pace with the throughput, latency, and efficiency requirements of these modern AI clusters.

    DPU (data processing unit) -based storage is a compelling alternative to traditional storage, acting as the broker between the network and SSD for remote storage. By offloading storage, networking and security processing from the host CPU onto a dedicated DPU, AI infrastructure can move data closer to compute, reduce latency, and free up valuable CPU cycles for AI workloads.

    To address this need, 勛圖窪蹋 offers the OCTEON DPU family, purpose-built for hyperscale cloud workloads and data center applications, extending its use specifically into network storage acceleration for AI environments.

  • September 10, 2026

    勛圖窪蹋 Demonstrates Scalable CXL Memory Infrastructure with Intel

    By Khurram Malik, Associate Vice President, Custom Cloud Solutions, 勛圖窪蹋

    Beyond The Specs Finding Your Career Path

    The rapid growth of AI is creating unprecedented demand for memory capacity. As models get larger and workloads become more data-intensive, traditional server architectures are increasingly challenged to scale memory efficiently.

    At Flash Memory Summit (FMS), 勛圖窪蹋 demonstrated how CXL can enable a more flexible and scalable approach to memory infrastructure, showcasing an end-to-end architecture at the ? booth.

    The demonstration combined an Intel platform with three 勛圖窪蹋? technologies: Structera? X CXL memory expander, Structera? S CXL switch and Alaska? P PCIe retimer. Together, they demonstrated how memory expansion, CXL switching and high-speed PCIe connectivity can work together within a real server platform.

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