Posts Tagged 'Optical Connectivity'
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November 05, 2026
³Ô¹ÏºÚÁÏ Earns LEAP Award for 1.6T Optical DSP Platform Portfolio
By Vienna Alexander, Marketing Content Professional, ³Ô¹ÏºÚÁÏ
Design World recently announced their . The ³Ô¹ÏºÚÁÏ? 1.6T optical DSP platform portfolio has been honored in the connectivity category.
³Ô¹ÏºÚÁÏ has decades of expertise in optical DSPs and ushered in the 1.6T era. The portfolio being honored was announced earlier this year and spans Ara T, Ara X, Aquila M and Petra.
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September 29, 2026
³Ô¹ÏºÚÁÏ Wins EDGE Award for COLORZ 1600 2nm 1.6T ZR/ZR+ Pluggable Optical Platform
By Vienna Alexander, Marketing Content Professional, ³Ô¹ÏºÚÁÏ
In the , the ³Ô¹ÏºÚÁÏ? COLORZ? 1600 2nm 1.6T ZR/ZR+ pluggable optical platform won the Machine Vision and Optical Components & Systems category.
Electronic Design presented this year¡¯s winners and honorees to celebrate recent design and engineering feats that excel in the industry. These innovations are pushing the bounds and represent the leading ¡°EDGE¡± of technology.
³Ô¹ÏºÚÁÏ COLORZ 1600 is the industry¡¯s first 1.6T ZR/ZR+ data center interconnect (DCI) pluggable. Powered by ³Ô¹ÏºÚÁÏ Electra, the industry¡¯s first 2nm 1.6T ZR/ZR+ coherent DSP, the device delivers efficient, high-performance and secure optical transmission for hyperscale AI and cloud networks globally. The pluggable is purpose-built for long-distance links; COLORZ 1600 connects campus (20km), metro (120km) and regional (1,000km) data centers at 1.6T.
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August 04, 2026
Photonic Fabric? Technology: How Optical Connectivity Enables the Next Generation of AI Infrastructure
By Ravi Mahatme, Senior Director, Product Management, Photonic Fabric Business Unit, ³Ô¹ÏºÚÁÏ
AI infrastructure is entering a new architectural era. As AI inference scales, performance increasingly depends not simply on adding more compute, but on how efficiently compute, memory and connectivity operate together as one unified AI infrastructure system. Modern AI inference workloads are insatiable consumers of memory. Large language models, reasoning models and agentic AI applications require rapid access to model parameters, embeddings and rapidly growing key-value (KV) caches that preserve conversational context. These working data sets are growing into the hundreds of gigabytes, and increasingly terabytes, making memory capacity, bandwidth and latency just as important as accelerator performance. As AI infrastructure scales, overall system performance increasingly depends on how efficiently accelerators can access, move and utilize memory resources rather than simply adding more compute.
Why AI Needs a New Memory Tier
Today's AI memory hierarchy was never designed for inference at the scale modern workloads demand. High bandwidth memory (HBM) attached directly to GPUs delivers exceptional performance but remains expensive and capacity constrained. System DRAM provides larger memory pools but cannot economically scale alongside every accelerator. NVMe SSDs offer abundant capacity, yet their latency makes them unsuitable for serving active inference workloads.
This challenge is especially visible in large language models, where growing KV caches must remain readily accessible to avoid repeatedly recomputing previous tokens. Keeping these caches entirely in HBM is prohibitively expensive, while moving them to storage introduces latency that reduces token generation performance. The result is that GPUs increasingly spend valuable cycles waiting for data rather than performing inference.
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May 19, 2026
Why Scale-up AI Networks Demand Scalable Optical Test
By Andrew Yick, Technical Associate Vice President, Operations Engineering, ³Ô¹ÏºÚÁÏ
This article was first published in magazine.
The dominant challenge in modern AI infrastructure is not just the performance of a?single accelerator but scaling up to thousands?of accelerators (XPUs) in a cluster. Training and inference workloads now depend on an interconnect that can stitch these accelerators into a high-bandwidth, low-latency system, where performance is governed as much by the network as by the compute itself.
As these systems scale, physics asserts itself. Electrical links over copper hit a practical ceiling as routing density and channel loss collide, turning the loss bandwidth product into an impassable constraint. The choice is binary: either move electrical-to-optical conversion closer to the Application-Specific Integrated Circuit (ASIC) or surrender the link budget. Thus, to bypass this electrical wall, optics must migrate from the board edge and onto the ASIC package.
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May 06, 2026
Scale-up Network Solutions for AI Infrastructure
By Preet Virk, Senior Vice President and General Manager, Photonic Fabric Business Unit
Modern AI infrastructure is built around multi-rack systems where thousands to tens of thousands of accelerators operate as a single logical compute element. As agentic AI and Mixture of Experts (MoE) models accelerate AI adoption, they are driving unprecedented scale and communication demands across data center infrastructure. These systems are connected by scale-up and scale-out networks that must deliver high bandwidth, low latency and efficient power. As these networks extend across racks, maintaining that performance becomes a primary challenge.
As AI systems grow in complexity and scale, the network becomes the backbone of the compute system. Large-scale clusters require massive XPU-to-XPU communication, driving an evolution beyond legacy protocols like PCIe? to encompass UALink? (Ultra Accelerator Link), ESUN (Ethernet scale-up networking) and NVLink.
Meeting these requirements demands a new approach to connectivity. ³Ô¹ÏºÚÁÏ provides a comprehensive AI connectivity portfolio spanning scale-up, scale-out, scale-across and DCI (data center interconnect) network architectures. For scale-up networking, ³Ô¹ÏºÚÁÏ delivers copper and optical interconnects connecting XPUs, switches and memory. Within the rack, ³Ô¹ÏºÚÁÏ copper solutions provide low-latency, power-efficient short-reach connectivity, while ³Ô¹ÏºÚÁÏ optical interconnects enable high-performance scaling beyond the rack. This enables XPUs to operate as a more efficient, unified system as scale-up domains expand.
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